In a conventional correlating device for use in spread spectrum communications, a method in which the correlation between an input signal and a binary-code sequence is calculated by converting the input signal in analog form into a digital signal (AD conversion) and then performing a digital operation, is mainly used. However, in this method, since an AD convertor is required, the circuit structure is complicated. Consequently, it is difficult to achieve a compact low-power-consuming correlating device with this method.
Therefore, for example, a correlating device which directly calculates the correlation by means of an analog circuit tends to be used as described in, for example, Japanese laid-open publication (Tokukaihei) No. 3-224329. For example, as shown in FIG. 9, in such a correlating device 101, an alternating current component of an analog input voltage Vin is converted into a current signal by a differentiating circuit 102, and then input to a switch 103. The current signal is input to an analog signal integrator 104 only when the switch 103 is closed. Here, closing and opening of the switch 103 is controlled by a binary-code sequence signal C.sub.-- PN given by a binary-code sequence generator 105. Thus, the correlating device 101 can give the correlation between the alternating current component of the input signal and the binary-code sequence with respect to time by calculating the sum of products of the alternating current component of the input signal and the binary-code sequence.
With this structure, the correlation can be calculated without converting the input signal into a digital signal. It is therefore possible to realize a correlating device that is more compact and consumes less power compared to a correlating device which requires an AD converter and calculates the correlation by a digital operation.
However, in the case when a correlating device is realized by an analog circuit, as the binary-code sequence becomes longer, it is more difficult to achieve both an improvement of the operation accuracy and a lowering of the power consumption.
More specifically, in order to retain the integrated value, the analog signal integrator 104 includes a capacitance such as a capacitor. Hence, the capacitance of the capacitor needs to be set at a value at which saturation does not occur before completing the correlation operation.
However, when integrating the correlating device into an IC (integrated circuit), it is difficult to make the capacitance of the capacitor greater than a certain value. When the capacitance is increased, the operable speed decreases unless the value of a current charged to and discharged from the capacitance is increased, i.e., the power consumption is increased. On the other hand, even when the capacitance is relatively small, in order to prevent saturation, the gain of the analog signal integrator 104 needs to be set at a small value. In this case, as the binary-code sequence length becomes longer, it is necessary to decrease the gain. Therefore, the S/N ratio of the analog signal integrator 104 is reduced, and the operation accuracy of the correlating device 101 is lowered.
Here, in order to improve the accuracy of calculating the correlation, a correlating device using a switched-capacitor-type analog signal integrator 111 shown in FIG. 10 and a multiplexer is also used. More specifically, in a correlating device 121 shown in FIG. 11, a sampling circuit 122 accumulates charge corresponding to the analog input signal Vin in a sampling capacitor C1 according to a sampling control signal C.sub.-- SP shown in FIG. 12. Moreover, a multiplexer 124 applies the accumulated amount of charge to the analog signal integrator 123 as it is or after inverting its sign according to a binary-code sequence signal C.sub.-- PN. The multiplexer 124 shown in FIG. 11 is connected to a negative input terminal and a positive input terminal of an operational amplifier A1 in an analog signal integrator 123 similar to the analog signal integrator 111 shown in FIG. 10.
In this structure, charge accumulated in a feedback capacitor C2 provided between the input and output of the operational amplifier A1 is discharged by a switch SW125 at the time a dump control signal C.sub.-- DP instructs to start the binary-code sequence. Thus, the correlating device 121 can output the correlation from a time point at which the dump control signal C.sub.-- DP instructs to start the binary-code sequence. Here, the correlating device 121 calculates the sum of products based on the analog input voltage Vin at the time of sampling. Consequently, the operation error due to a variation in the analog input voltage Vin at times other than sampling can be reduced, thereby improving the operation accuracy.
However, even in the correlating device 121 having the above-mentioned structure, if the gain of the analog signal integrator 123 is not made smaller as the binary-code sequence length increases, the feedback capacitor C2 saturates.
More specifically, if C1 is decreased to reduce the gain (C1/C2) of the analog signal integrator 123, the S/N ratio of the correlating device 121 deteriorates due to clock field through noise (to be described later), ktC noise, etc. The ktC noise is generated by thermal noise of the switch in the sampling circuit 122. On the other hand, if C2 is increased to reduce the gain, the load capacitance of the operational amplifier A1 increases. Thus, if the power consumption of the operational amplifier A1 is not increased, the operation speed of the analog signal integrator 123 is lowered.
More specifically, denoting the length of binary-code sequence by n, when the analog input voltage Vin of signal amplitude .vertline.Vin.vertline. and the binary-code sequence have the maximum correlation, the output voltage of the analog signal integrator 123 is a maximum Vmax [V] given by equation (1): EQU Vmax=n.multidot.C1/C2.multidot..vertline.Vin.vertline. (1).
Therefore, if the value Vmax is not within a range of voltage that can be output by the analog signal integrator 123, the correlating device 121 can not output an accurate correlation.
Here, it is arranged as an example that the sequence length n is 128, the range of voltage that can be output by the analog signal integrator 123 is 1.5 [V].+-.1.0 [v], the reference electric potential of the analog input voltage Vin is 1.5 [V], and the amplitude of the analog input voltage Vin is .+-.1 [V]. In this case, for example, when the sampling capacitor C1 is set at 1 [pF], the feedback capacitor C2 of the analog signal integrator 123 needs to satisfy the relation C2&gt;128 [pF] because the maximum Vmax+1.5 [V]&lt;2.5 [V]. The feedback capacitor C2 is an output load of the operational amplifier A1, and causes a lowering of the operation speed or an increase in the power consumption.
Meanwhile, under the same conditions, when the feedback capacitor C2 is set at, for example, 5 [pF], the capacitance of the sampling capacitor C1 is limited to C1&lt;0.019 [pF]. Here, in the case where the switch of the sampling circuit 122 is formed by a CMOS (metal oxide semiconductor), if the gate length and gate width of NMOS is 1 [.mu.m] and 2 [.mu.m] and the gate length and gate width of PMOS is 1 [.mu.m] and 4 [.mu.m], respectively, the sum of the parasitic capacitance between the gate and source of the two MOSs is approximately around 5 [fF] to 10 [fF]. Accordingly, the ratio of the capacitance of the gate parasitic capacitor of a transistor constituting both the switches to the capacitance of the sampling capacitor C1 is less than one figure. As a result, the S/N ratio of the analog signal integrator 123 is lowered due to a phenomenon that the charge accumulated in the gate parasitic capacitor is mixed with charge accumulated in the sampling capacitor at the time the switch is opened or closed, i.e., the clock field through phenomenon.
In spread spectrum communications as a suitable application of a correlating device, the communication speed is increasing and the length of binary-code sequence is being made longer. Furthermore, since the terminals for communications are often carried, there is great demand for a lowering of power consumption.
However, as described above, in the conventional correlating devices 101 and 121, when calculating the correlation between an input signal and a lengthy binary-code sequence at a high speed, it is extremely difficult to avoid both of a lowering of the operation speed and an increase in the power consumption.